Description
NVIDIA is hiring an experienced ASIC Floorplan Engineer to design and implement floorplans for SOCs, CPUs, and GPUs from early architecture through physical design. The role partners with product, architecture, ASIC, physical design, and packaging teams to optimize cost, area, performance, power, interconnect, timing, and risk mitigation, while developing AI workflows and productivity tools. Candidates need an MSEE/MSCE or equivalent experience, at least 10 years of chip development experience, broad ASIC and physical-design expertise, and experience with Python, Perl, or C++. The base salary range is 196,000 USD to 310,500 USD, with equity and benefits, and applications were accepted until June 25, 2026.
