Senior ASIC Floorplan Design Engineer at NVIDIA

Department: Engineer, ASIC

Compensation

$196,000 – $310,500/yr

Setup: On-site
Location: California · Austin, Texas
Type: Full-time
Level: senior
Posted: May 21, 2026

Description

NVIDIA is hiring a Senior ASIC Floorplan Design Engineer to develop and optimize floorplans during early SoC and GPU development, collaborate with architects and physical-design leads, drive area and interconnect reviews, resolve timing and routing-congestion issues, and build tools to improve chip area and execution speed. The role requires a master's degree in electrical, computer, or computer engineering, at least 12 years of relevant experience, VLSI or computer-architecture expertise, hardware-description-language experience, physical-design and floorplan knowledge, and Python, Perl, and C/C++ programming experience. The base salary range is 196,000 USD to 310,500 USD for Level 5 and 232,000 USD to 368,000 USD for Level 6, with equity and benefits; applications were accepted until May 25, 2026.

Required Skills

VLSI
Computer Architecture
Verilog
System Verilog
Chip floorplan
Power distribution
P&R
Timing closure
Python
Perl
C/C++

Additional Information

Minimum Education: Master's degree in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent experience
Required Previous Experiences: At least 12 years of relevant work experience
Experience with Verilog, System Verilog, or similar hardware description languages
Experience with CAD and physical-design methodologies, chip floorplan, power and clock distribution, packaging, P&R, and timing closure
Experience with Python, Perl, and C/C++ programming
Preferred Qualifications: Experience driving development of large-scale ASIC floorplans
Translation Company Name: NVIDIA