Senior ASIC Timing Engineer, DFT at NVIDIA

Department: Engineer, ASIC

Compensation

$136,000 – $264,500/yr

Setup: On-site
Location: California
Type: Full-time
Level: senior
Posted: Aug 11, 2026

Description

NVIDIA is hiring a DFT-Timing Engineer to drive timing analysis and closure for DFT logic across GPUs, CPUs, DPUs, LPUs, and SoCs. The role involves developing timing constraints, collaborating with design and verification teams, fixing timing paths through ECOs, improving automation and standardization, and supporting timing and power convergence. Candidates need an electrical or computer engineering background with the specified experience levels, hands-on STA and full-chip/sub-chip timing convergence experience, ECO expertise, and knowledge of industry timing tools. The base salary range is 136,000–218,500 USD for Level 3 and 168,000–264,500 USD for Level 4, with equity and benefits; applications were accepted until August 15, 2026.

Required Skills

Static Timing Analysis
Timing Convergence
ECOs
Timing Constraints
DFT Logic
Automation

Additional Information

Minimum Education: Bachelor of Science in Electrical or Computer Engineering with 5+ years of experience, or Master of Science with 2+ years of experience
Required Previous Experiences: Hands-on experience in Static Timing Analysis and full-chip/sub-chip timing convergence at advanced technology nodes
Expertise in analyzing and fixing timing paths through ECOs
Expertise in developing timing constraints
In-depth knowledge of industry-standard timing convergence tools
Preferred Qualifications: Understanding of DFT logic and experience with DFT timing closure across scan, iJTAG, and other modes
Background in domain-specific STA and timing convergence, including SerDes, processor, IO, and SMVA
Experience in methodology and workflow development