Description
The company is hiring a Senior ASIC Verification Engineer to lead verification of Netpreme silicon, IP, and subsystems from microarchitecture through tapeout. The role provides technical leadership, defines verification methodologies, guides design optimization for performance, power, and area, and coordinates with architecture, design, physical design, firmware, DFT, post-silicon, and external IP, foundry, and EDA teams. It is an onsite position in Santa Clara, California, or Boston, Massachusetts, with a bachelor’s or master’s degree, at least five years of ASIC/SOC verification experience, and strong verification, protocol, and PPA expertise.
