Senior ASIC Verification Engineer, Lund at Axis Communications Aktiebolag

Language

Location: Lund
Type: Full-time
Level: senior
Posted: Sep 15, 2026

Description

Axis is hiring a Senior ASIC Verification Engineer to perform pre-silicon verification of in-house hardware IPs and subsystems, including ARTPEC SoCs. The role uses simulation and formal methods, requires expertise in Verilog, SystemVerilog, UVM, SoC architecture, Python or Tcl, and embedded microprocessor verification, and involves debugging, advanced verification environments, and evaluation of new verification technologies.

Required Skills

Verilog HDL
SystemVerilog
UVM
SoC architecture
Python
Tcl
Embedded microprocessors
Formal verification

Additional Information

Minimum Education: Bachelor's or Master's degree in Computer Science, Electrical/Computer Engineering, or a related field
Required Previous Experiences: Experience developing sophisticated compute subsystems or SoCs from specification and modelling through tape out
Experience with complex SoC architecture and multi-clock, AXI/APB, multi-power, and reset architectures
Experience with Python, Tcl, or another scripting language
Experience verifying SoC projects or systems involving embedded microprocessors
Preferred Qualifications: End-to-end formal verification and formal property verification
Clock domain crossing and connectivity verification
Power-aware verification
Transaction-level modeling and SystemC
Translation Company Name: Axis Communications Aktiebolag