Description
MittLogik Group is hiring a Senior ASIC Verification Engineer to own the verification lifecycle for complex 5G, 6G, and next-generation hardware. The role covers UVM and SystemVerilog testbench architecture, end-to-end SoC and IP verification, constrained-random and assertion-based testing, C-based embedded software testing, hardware emulation, and continuous-integration regression suites. The engineer will collaborate with RTL designers, mentor junior engineers, and influence architectural decisions. A bachelor’s or master’s degree in a relevant engineering or computer science field and at least 10 years of ASIC/SoC and IP-level verification experience are required, with telecommunications or semiconductor industry experience preferred. The position offers relocation support and visa sponsorship for talent joining the company in Sweden.
