Description
Google is hiring a Senior CAD Engineer to lead CAD methodology engineers supporting RTL design teams, standardize chip design methodology, evaluate design tools, and lead end-to-end chip design process improvement projects. The role also involves design reviews, issue resolution, and technical trade-off discussions. Candidates need a bachelor's degree in electrical engineering or a related field or equivalent practical experience, 8 years of experience with SystemVerilog, hardware design, automation, and design verification testing, and 5 years of CAD experience. Preferred qualifications include an advanced degree, experience deploying new tools and flows, knowledge of RTL quality methodology, and the ability to present novel methods. The position offers $163,000–$236,000 USD plus a 15% bonus target, equity, and benefits.
