Description
SiFive is hiring a Senior Design Formal Verification Engineer to own formal verification strategies for advanced out-of-order CPU cores. The role involves identifying verification targets, creating formal test plans, maintaining Chisel-based formal environments, applying formal techniques, debugging RTL, automating verification, reviewing proofs, and training team members. Candidates need at least five years of formal verification experience, extensive formal abstraction and sign-off experience, familiarity with tools such as VC Formal and JasperGold, and knowledge of VHDL, Verilog, or SystemVerilog.
