Senior Debug Verification Engineer at Altera

Altera is hiring a Sr. Debug Design Verification Engineer in San Jose, California, to perform pre-silicon SoC, FPGA, and full-chip design verification, including UVM testbench creation, verification strategy and test-plan development, and cross-functional coordination with design, software, and architecture teams. The role requires at least eight years of experience with complex ASIC designs or verification, SystemVerilog, UVM, and formal verification, with additional experience in JTAG, high-speed USB, PCIe, ARM, RISC, emulation, and UltraSoC/Tessent Embedded Analytics Debug Architecture preferred or advantageous. The regular shift is Shift 1 in the United States, with a Bay Area salary range of $149,100 to $215,000 USD.