Senior Design-for-Test (DFT) Engineer at E-Space

E-Space is hiring a Senior Design-for-Test (DFT) Engineer for its SoC design team to define and implement DFT architectures and strategies for complex digital SoCs supporting 5G, IoT, and LEO satellite communications. The role covers scan insertion, ATPG, fault simulation, BIST, ATE test-program development, DFT automation, sign-off verification, and collaboration with physical design and STA teams. It is a full-time, exempt position based in Saratoga with a target base pay of $120,000 to $220,000 annually and requires at least eight years of DFT experience for complex digital ASICs or SoCs.