Senior Design-for-Test (DFT) Engineer at Intel

Intel is hiring an experienced Design-for-Test (DFT) engineer in Bangalore, India to design, implement, validate, and debug DFT solutions for IP and SoC programs. The role covers TAP/JTAG, IJTAG, Boundary Scan, MBIST, scan insertion and compression, ATPG, RTL and gate-level simulation, test collateral, coverage optimization, silicon debug, and DFT signoff. It requires collaboration across design, verification, physical design, product engineering, manufacturing test, and IP teams, plus technical leadership and process improvement. The position follows a hybrid work model.