Senior Design Verification Engineer at Astera Labs

Astera Labs is hiring a Senior Design Verification Engineer to develop and execute verification strategies for next-generation rack-scale AI connectivity silicon. The role focuses on PCIe, UALink, and UCI switching behavior, including UVM-based SystemVerilog testbenches, coverage closure, regression automation, debugging, and silicon readiness. Candidates need a bachelor’s degree in a relevant technical field and 2–5 years of ASIC or SoC design verification experience, with familiarity with simulation, waveform debugging, and coverage tools.