Description
Astera Labs is hiring a Senior Design Verification Engineer to build and validate complex connectivity silicon for rack-scale AI infrastructure. The role focuses on UVM-based verification environments, SystemVerilog and C/C++ integration, directed and constrained-random testing, assertions, coverage, verification infrastructure, and debugging across simulation, co-simulation, and FPGA-based emulation. The engineer will collaborate with RTL designers and other engineers to resolve failures and manage verification deliverables.
