Description
proteanTecs is hiring a Senior Design Verification Engineer to join a global team of Application Engineers. The role focuses on integrating proteanTecs IP and design-verification flows into customer designs, debugging RTL and gate-level issues, supporting signoff, reproducing customer problems, and correlating pre-silicon and post-silicon behavior. The engineer will also create application notes and integration guides, provide feedback to R&D and Product Management, and support feature validation and early-access programs. The position requires a bachelor’s or master’s degree in electrical or computer engineering or a related field, at least three years of experience, and proficiency with SystemVerilog/UVM, advanced testbench architecture, flow automation, and digital design.
