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Senior Design Verification Engineer - Hardware at NVIDIA

Department: Engineer, ASIC

Language
Setup
On-site
Location
Huangpu, Shanghai
Type
Full-time
Level
senior
Posted

Description

NVIDIA is hiring a Verification Engineer for its Shanghai MMPLEX team to verify hardware intellectual property. The role involves developing verification methodology, test plans, UVM-based testbenches, regression flows, coverage models, full-chip SOC verification, failure triage, and coverage analysis. Candidates need an MS in electrical or computer engineering or equivalent experience, at least five years of experience, and strong knowledge of Verilog and high-level verification languages, with Python, C/C++, Perl, Shell, or Ruby programming skills preferred.

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