Description
The Senior Design Verification Engineer will define verification methodology and implement test plans for advanced hardware functional blocks, collaborate with architecture, RTL, product design, software, and validation teams, and contribute to simulation and emulation bringup. The role involves creating SystemVerilog and UVM verification environments, developing test plans and coverage measures, debugging RTL and testbench issues, performing UPF-based low-power verification, automating DV methodologies, and building system-level performance-analysis infrastructure. Candidates need a bachelor's degree in electrical engineering or a related field, extensive semiconductor ASIC experience, and experience with verification platforms, scripting, object-oriented design, and RTL development environments.
