Senior Development Engineer - Density Fill at Intel

Compensation

$128,880 – $245,160/yr

Setup: Hybrid
Location: Hillsboro, Oregon · Santa Clara, California · +2
Type: Full-time
Level: not_specified
Posted: Sep 23, 2026

Description

Intel is seeking an experienced EDA Tools Software Engineer to join their Design Technology Platform (DTP) organization. The successful candidate will be responsible for designing, developing, testing, and debugging software tools and methodologies to support Intel's hardware product design and manufacturing processes. This role involves providing algorithmic solutions, automating workflows, developing test cases, and innovating in EDA tools to advance Intel's advanced process technologies.

Required Skills

Calibre
ICV
Pegasus
SVRF
TVF
PXL
PVL/PVTCL
Unix/Linux platforms
semiconductor device physics
process technology
design rules

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 8+ years of experience, Master's degree with 5+ years of experience.
Required Previous Experiences: Minimum 5 years of hands-on experience with at least one industry-standard physical verification platform (Calibre, ICV, or Pegasus), including methodology development, rule deck debugging, or production deployment.
3+ years of direct experience developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, or PVL/PVTCL for DRC, density, or fill verification applications.
Preferred Qualifications: 5+ years of hands-on experience developing, deploying, or supporting density fill methodologies for semiconductor technologies at 16nm and below, including ownership of fill rule implementation, density compliance, or manufacturability optimization.
Experience with advanced physical verification techniques, including DRC, and density/fill modules.
Industry experience with other foundry technologies in this domain is strongly desirable
Familiarity with custom layout tools such as Cadence Virtuoso or Synopsys Custom Designer.
Deep understanding of technology scaling challenges and their impact on physical design rules.
Proven track record of collaborating across multiple internal and external teams to deliver optimal solutions.
Exceptional analytical and problem-solving skills with the ability to address cross-disciplinary challenges.
Strong written and verbal communication skills, with the ability to present complex technical concepts clearly.
Leadership experience driving innovation, process improvements, or cross-functional initiatives.
Strong preference for candidates with experience from semiconductor foundries, advanced packaging organizations (OSATs), integrated device manufacturers (IDMs), or EDA vendors, where they have contributed to physical verification, density-fill methodology development, process design kits (PDKs), or manufacturing-driven design solutions.