Description
The Senior DFT Design Engineer will define and implement DFT architecture and flows for Google’s TPU and AI/ML hardware, including hierarchical DFT, boundary scan, scan chains, compression, BIST, TAP controllers, and other DFT IP. The role covers TDRC validation, design changes, test documentation, production and debug pattern delivery, and post-silicon support. Candidates need a bachelor’s degree in electrical engineering or a related field, equivalent practical experience, and 8 years of DFT implementation and validation experience.
