Description
Astera Labs is expanding its R&D center in Israel, focusing on developing complex semiconductor chips to address data bottlenecks in AI at scale. The company is seeking a Senior DFT Engineer to join this new site and take ownership of the reliability and testability of chips that power large AI clusters. This role involves defining DFT architecture, developing and optimizing test patterns, and collaborating with various teams to ensure seamless integration and optimal quality of results. The engineer will be crucial in establishing world-class DFT methodologies for deep-submicron processes.
