Description
NVIDIA is hiring a Design-for-Test Engineer to develop and deploy DFT architectures, test access mechanisms, IO and memory BIST, scan compression, and verification methodologies for complex semiconductor chips. The role also involves mentoring junior engineers and collaborating with cross-functional teams across RTL, clocks, STA, place-and-route, and power. Candidates need a BSEE or equivalent experience, MSEE with at least three years of experience, or a PhD in DFT or a related domain, along with expertise in scan testing, BIST, fault modeling, ATPG, fault simulation, silicon debug, and ATE bring-up. The posting is hybrid and offers a base salary of 136,000–218,500 USD for Level 3 and 168,000–264,500 USD for Level 4, plus equity and benefits.
