Description
The DfT Engineer will collaborate with product and design teams to define testability requirements for analog, mixed-signal, standard macro, and complex digital IP. The role covers RTL design in Verilog and System-Verilog, verification planning, test development, debug, scan insertion, optimization, P&R-aware rerouting, ATPG, silicon debugging, customer-return support, design reviews, and DfT documentation. Candidates need a Master of Science in Electrical Engineering with relevant digital design and DfT coursework, at least three years of experience in a similar DfT, digital design, or architecture role, and willingness to relocate to the Phoenix metro area with at least three full-day days per week in NXP's Chandler office.
