Description
NVIDIA is hiring a Senior DFT Methodology Engineer to architect and develop test methodologies for next-generation semiconductor products. The role covers test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, memory dump, and DFX security; partners with timing, physical design, software, bring-up, and production teams; and mentors junior engineers. Candidates need a BS/MS in electrical or computer engineering or equivalent experience, at least 10 years of SoC architecture, RTL design, and verification experience, and expertise in silicon debug, ATE, and test pattern development. The posting is marked hybrid and accepts applications through September 22, 2026.
