Description
Astera Labs is hiring a Senior Digital Design Engineer to design and integrate high-performance connectivity silicon for AI infrastructure. The role covers digital architecture, RTL implementation, synthesis, timing closure, IP integration, and design quality for PCIe, Ethernet, SerDes, bridges, switches, and related controllers. The engineer will work across block-level and full-chip development at advanced process nodes, collaborate with verification, physical design, DFT, firmware, and system teams, and use Synopsys, Cadence, Python, or Perl to improve productivity and automation. A bachelor’s degree in electrical or electronics engineering and 2–5 years of digital design experience are required; the salary range is $139,500 to $155,000 CAD.
