Description
Texas Instruments is hiring a Design Verification Engineer to verify analog and mixed-signal electronic designs before pattern generation and mask development. The role develops verification strategies, UVM environments, testbenches, simulations, coverage models, and formal verification; executes RTL and gate-level testing; debugs design and testbench issues; and supports ATE pattern generation and silicon characterization. It requires a master's or bachelor's degree in electrical engineering, at least five years of experience, and expertise in SystemVerilog, UVM, formal verification, CDC/RDC, and low-power verification, with additional automation and mixed-signal capabilities preferred.
