Description
NVIDIA is hiring a Senior Digital Design Verification Engineer to verify SerDes IP designs, golden models, and micro-architectures using UVM and coverage-driven verification. The role involves building reusable bus models, monitors, checkers, and scoreboards; defining verification scope; developing verification infrastructure; and validating designs under product-shipment schedules. Candidates need a bachelor's or master's degree in a relevant engineering or computer science field, at least five years of validated experience, and expertise in SystemVerilog, random stimulus, functional coverage, assertions, and UVM/VMM. The posting lists base salary ranges for Level 3 and Level 4 and states that applications were accepted until April 12, 2026.
