Senior Digital Verification Engineer at Efficient Computer

Department: Verification & Emulation

Compensation

$160,000 – $210,000/yr

Location: San Francisco, Texas
Type: Full-time
Level: senior
Posted: Sep 1, 2026

Description

Efficient is hiring an experienced Design Verification Engineer to lead functional verification of complex SoC/IP designs from specification through tapeout on a newly formed verification team. The role requires extensive ASIC/SoC design verification experience, UVM and SystemVerilog expertise, C/C++ modelling or verification experience, coverage closure, simulation debugging, and Python test automation. The position offers a base salary of $160,000 to $245,000, a 10% annual bonus, equity, and comprehensive benefits.

Required Skills

UVM
SystemVerilog
C/C++
Coverage Closure
Python
Formal Verification
UPF

Additional Information

Minimum Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field
Required Previous Experiences: 10+ years of progressive ASIC/SoC design verification experience with multiple full cycles from testbench architecture through tapeout
Experience driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs
Preferred Qualifications: Formal verification experience with JasperGold or similar
Experience building or using AI agentic flows for design verification
Software or firmware testing experience working with software teams pre-silicon
Post-silicon experience
SoC architecture experience with processors, interconnects, memory controllers, DMA engines, interrupt controllers, or standard peripherals
Power-aware verification and UPF experience
Translation Company Name: Efficient Computer