Description
NXP is hiring a Digital Verification Engineer to lead verification of post-quantum cryptography and security IP, including secure SoC subsystems and high-assurance cryptographic accelerators. The role combines traditional hardware verification with AI-driven automation, covering SystemVerilog/UVM environments, constrained-random and metrics-driven verification, coverage closure, SVA, debugging, and collaboration with design and architecture teams. Candidates need a BSc. or MSc. in Electronics or Electrical Engineering and strong experience with SystemVerilog, UVM, constrained-random verification, metrics-driven verification, coverage closure, and debugging.
