Description
Renesas is seeking a Senior Digital Verification Engineer to lead end-to-end verification of complex IC blocks and systems. The role owns verification strategy, UVM-based environments, functional and code coverage, specification quality, cross-functional collaboration, technical leadership, and make/buy decisions for verification tools. Candidates need extensive ASIC/IC digital verification experience, strong SystemVerilog and UVM expertise, proficiency with simulators and management tools, and knowledge of functional, assertion-based, formal, and regression verification methodologies.
