Description
ST is hiring a Digital Verification Engineer – SoC in Naples to develop and maintain SystemVerilog UVM testbenches, C firmware and drivers, and Python automation scripts for complex SoC and IP used in automotive and industrial applications. The role covers verification strategy, simulation and emulation, functional and coverage debugging, gate-level timing analysis, AI-assisted workflows, and verification documentation. Candidates need a relevant engineering degree, 5–8 years of experience, strong SystemVerilog/UVM and C skills, Python and Unix/Linux knowledge, familiarity with major digital simulators, and good English.
