Description
The role is responsible for architecting, implementing, and validating DFT techniques on ARM SoCs, including RTL and gate-level DFT insertion, ATE test-pattern generation, and silicon characterization. It requires core DFT skills such as scan compression, BIST, JTAG, ATPG, fault simulation, and silicon debug, along with Verilog, TCL or Perl, Unix/Linux, and a bachelor’s or master’s degree in a relevant engineering field. The position offers a hybrid working arrangement and experience ranges from 3 to 20 years.
