Description
Microchip Technology Inc. is hiring a Physical Design Engineer for its AES Design team in Bangalore, India. The role owns RTL-to-GDSII physical design for large and complex SOC blocks and subsystems across 40nm to 3nm and below technology nodes, including floorplanning, place-and-route, timing closure, physical verification, IR and EM checks, IP integration, and hierarchical design. The engineer will use Innovus or ICC2 and other backend tools, lead junior team members, communicate with implementation and project teams, and may travel 0–25% of the time.
