Senior Engineer II - Physical Design at Microchip - USA

Language

Compensation

CA$86,000 – CA$186,000/yr

Location: Burnaby, British Columbia
Type: Full-time
Level: senior
Posted: Sep 16, 2026

Description

Microchip Technology Inc. is hiring a Senior Physical Design Engineer for its Implementation team in the Burnaby, British Columbia office. The role focuses on ASIC and SOC physical design, including block-level place and route, physical verification, test structures, digital wrappers, synthesis, and static timing. The engineer will support customers through Microchip’s chip development flow and collaborate with CAD, packaging, mixed-signal, operations, and design teams. The position requires an electrical or electronics engineering degree, at least 7.5 years of ASIC development experience, and proficiency with physical design flows, Verilog or VHDL, and Python, Perl, or TCL scripting. The annual base salary range is $86,000 to $186,000, with travel time of 0–25% and health benefits beginning on day one.

Required Skills

Physical verification
Place and route
Static timing
Floorplanning
Clock synthesis
Verilog
VHDL
Python
TCL scripting

Additional Information

Minimum Education: At least a four-year degree in Electrical or Electronics Engineering
Required Previous Experiences: At least 7.5 years of ASIC development experience in a fast-paced environment
Hands-on experience with physical design flows, including floorplanning, placement optimization, clock tree synthesis, and physical verification
Recent experience leading full-chip physical design activities
Experience implementing chip-level, subsystem, CPU, and mixed-signal blocks
Ability to understand Verilog and VHDL languages
Proficiency in Python, Perl, or TCL scripting
Preferred Qualifications: Experience with 6nm processes or lower