Description
The role is responsible for low-power structural verification, UPF implementation, power-aware equivalence checking, RTL-to-Gate and Gate-to-GDS signoff, logic equivalence checking, and automation of verification flows using Cadence Conformal Low Power, Synopsys VCLP, and Cadence Conformal LEC. The position requires 5+ years of relevant experience in logical signoff and low-power structural verification for sophisticated SoC and IP development programs, along with strong knowledge of UPF/CPF, SystemVerilog, and low-power verification tools. The role is part of Arm’s Solutions Engineering group and follows a hybrid working arrangement.
