Description
Astera Labs is hiring a Senior Physical Design Engineer to support next-generation transceiver IPs targeting TSMC 3nm and advanced nodes. The role involves block-level and top-level physical implementation, including floorplanning, placement, CTS, routing, physical verification, timing closure support, and ECO/tapeout signoff activities. The engineer will collaborate with RTL and STA teams, handle EM/IR and congestion optimization, ensure DRC/LVS/ANT/ERC clean signoff, use tools such as ICC2, Innovus, Voltus, RedHawk, and Calibre, and develop automation scripts in Tcl, Python, or Perl. A bachelor’s or master’s degree in an engineering-related field and 5+ years of physical design experience are required.
