Description
The role is responsible for synthesizing, physically designing, and implementing Arm cores, systems, and SoCs; leading synthesis and constraint development; analyzing timing, area, and power; developing implementation and data-mining methodologies; and supporting automation with Python. It requires a master’s degree equivalent in a relevant technical field and at least 8 years of ASIC implementation experience from RTL to GDS, including timing closure, tape-outs, ECOs, and signoff. The position offers a hybrid working arrangement.
