Senior Engineer, PLL Design at Samsung Semiconductor

Department: S.LSI (R&D)Education: education_required

Compensation

$138,000 – $206,000/yr

Location: San Jose, California
Type: Full-time
Level: senior
Posted: Sep 22, 2026

Description

Samsung Semiconductor Inc. is hiring a Senior/Staff PLL Designer to design and develop high-performance PLL and clocking subsystems for RF transceivers, SerDes, and high-speed I/O applications in advanced deep-submicron CMOS technologies. The role covers PLL and clock-generation circuit design, system-level modeling, noise and jitter analysis, verification, silicon bring-up, characterization, and collaboration with digital, layout, and systems teams. Candidates need a bachelor’s degree with 5+ years of experience, a master’s degree with 3+ years, or a PhD with 0 years of experience, along with extensive PLL design experience, IC design tool proficiency, and strong analysis and communication skills. The base pay range is $138,000–$206,000 USD.

Required Skills

PLL design
Clock generation
RF transceivers
SerDes
Matlab/Simulink
Spectre
Verilog/SystemVerilog
Phase noise
Jitter analysis

Additional Information

Minimum Education: Bachelor’s degree with 5+ years of experience, or a master’s degree with 3+ years of experience, or a PhD with 0 years of experience in a related field
Required Previous Experiences: Extensive hands-on PLL design experience in deep-submicron CMOS, including integer-N, fractional-N, digital, or sub-sampling PLL topologies
Laboratory characterization experience with phase noise, jitter, and spectrum analysis equipment
RTL design experience implementing PLL-related digital calibration circuits
Translation Company Name: Samsung Semiconductor