Description
The role supports functional and test-mode timing development, performs block and subsystem timing analysis, investigates setup and hold violations, generates and validates timing ECOs, reviews timing reports across modes and corners, and supports timing signoff and debugging. It requires STA fundamentals, hands-on PrimeTime or Tempus experience, physical design and timing ECO knowledge, multi-mode multi-corner analysis, scripting in TCL, Perl, or Python, and 2–4 years of Physical Implementation, STA, or Timing Signoff experience.
