Description
Google is hiring a Senior Engineer to develop and validate TPU machine-learning accelerator ASICs. The role owns hardware-software integration and validation, brings up ML compute features, develops validation firmware, uses RTL, emulation, and FPGA environments, creates microbenchmarks and test plans, and coordinates debugging across design, verification, software, architecture, compiler, and performance teams. The position requires a bachelor's degree in a relevant technical field and five years of experience in computer architecture, embedded firmware, ASIC design or verification, or first- or third-party IP integration, along with hardware-software integration and RTL development experience. Preferred qualifications include a master's or PhD, C++/Python software design experience, accelerator system integration, embedded firmware development, simulation-based debugging, and RTOS knowledge. Compensation is $163,000–$236,000 USD plus a 15% bonus target, equity, and benefits.
