Senior FPGA/SDR Engineer at Axon

Department: 2013 Axon Foundation Services

Compensation

$141,000 – $225,600/yr

Setup: Hybrid
Location: Boston, Massachusetts
Type: Full-time
Level: senior
Posted: Aug 31, 2026

Description

Axon is hiring a Senior FPGA/SDR Engineer to own the FPGA realization of digital signal processing for software-defined radio, including OFDM modem development, MATLAB/Simulink behavioral modeling, RTL generation, Vivado implementation, on-chip interfaces, verification, RF integration, and hardware bring-up. The role is based in Boston or Scottsdale on a hybrid schedule requiring onsite work Tuesday through Friday, with remote work on Mondays. It requires a bachelor’s degree in an engineering discipline and 6+ years of FPGA/RTL design experience, with a base pay range of $141,000 to $225,600 USD.

Required Skills

FPGA/RTL design
VHDL/Verilog
Vivado
MATLAB/Simulink
DSP
Digital communications
AXI4
HDL Coder
RTL verification
FPGA bring-up

Additional Information

Minimum Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or a similar engineering discipline
Required Previous Experiences: 6+ years of industry FPGA/RTL design experience
Experience with MATLAB/Simulink algorithm modeling and model-based design
Experience with fixed-point arithmetic and quantization analysis
Experience with on-chip interconnects, AXI4, DMA, and clock-domain crossing
Experience with RTL verification, testbenches, and HDL simulation
Experience with FPGA system bring-up and hardware debugging
Preferred Qualifications: Master’s or PhD in Electrical Engineering, Communications, or Signal Processing
Production experience with HDL Coder or equivalent high-level synthesis
Experience implementing OFDM modems and channel coding in hardware
Experience with Zynq UltraScale+ MPSoC and heterogeneous SoC/FPGA platforms
Experience integrating wideband RF transceivers and digital pre-distortion
Familiarity with GNU Radio and over-the-air testing
Experience with Git and CI for HDL and model-based design
Experience applying AI coding assistants to FPGA/HDL workflows