Senior FPGA/SDR Engineer at Axon

Department: 2013 Axon Foundation Services

Setup: Hybrid
Location: Scottsdale, Arizona
Type: Full-time
Level: senior
Posted: Aug 31, 2026

Description

Axon is hiring a Senior FPGA/SDR Engineer to own the FPGA realization of digital signal processing for its software-defined radio and mesh networking products. The role covers OFDM modem development, MATLAB/Simulink behavioral modeling, HDL Coder RTL generation, Vivado implementation, on-chip interfaces, verification, RF integration, hardware bring-up, and cross-functional collaboration. It is based in Boston or Scottsdale on a hybrid schedule requiring onsite work Tuesday through Friday, with remote work on Mondays unless an approved accommodation is granted. The position requires a bachelor’s degree in an engineering discipline and at least six years of FPGA/RTL design experience, with preferred qualifications including advanced degrees, HDL Coder, OFDM, Zynq UltraScale+, RF transceiver, and AI-assisted development experience.

Required Skills

FPGA design
MATLAB/Simulink
Vivado
VHDL/Verilog
OFDM
AXI4
HDL Coder
Digital communications
RTL verification
RF transceiver

Additional Information

Minimum Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or a similar engineering discipline
Required Previous Experiences: 6+ years of industry FPGA/RTL design experience from architecture through synthesis, timing closure, and hardware bring-up
Experience with MATLAB and Simulink for algorithm modeling and model-based design workflows
Experience with fixed-point arithmetic and quantization analysis
Experience with on-chip interconnects, AXI4/AXI4-Stream, DMA, memory interfaces, and clock-domain-crossing design
Strong RTL verification experience with testbenches, HDL simulation, and golden-model verification
Hands-on FPGA and system bring-up and debug experience with laboratory tools
Preferred Qualifications: Master’s or PhD in Electrical Engineering, Communications, or Signal Processing
Production experience with HDL Coder or equivalent high-level synthesis and model-to-RTL workflows
Hands-on experience implementing OFDM modems, channel coding, MIMO, channel estimation, and synchronization in hardware
Experience designing on Zynq or Zynq UltraScale+ MPSoC or other heterogeneous SoC/FPGA platforms
Experience integrating wideband RF transceivers and supporting RF impairment correction
Familiarity with software-defined radio platforms and over-the-air testing
Experience with Git and CI for HDL or model-based design
Experience applying AI coding assistants to FPGA/HDL workflows