Description
NVIDIA is hiring a Power Optimization and Analysis Engineer for its Switch u/arch team to analyze full-chip and unit-level power data, develop and deploy power-analysis methodologies, and collaborate with architects, ASIC, performance, software, and physical design teams to improve the power efficiency of next-generation switches. The role involves pre-silicon gate-level and RTL power analysis, workload selection, power-bug identification, architectural feature prototyping in Verilog, and automation using Python, Perl, and C++.
