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Senior Full Chip Layout Engineer at NVIDIA

Department: Engineer, ASIC

Language
Setup
On-site
Location
Yoqneam Illit, North District · Tel Aviv, Tel-Aviv District
Type
Full-time
Level
mid
Posted

Description

NVIDIA is hiring a Physical Design Engineer for its Networking Silicon engineering team to perform full-chip physical layout, integration, pinning, bump routing, and physical verification from floorplanning through tape-out. The role requires an Electronics Engineer certificate or B.Sc. in Electrical Engineering, five years of full-chip layout and physical verification experience, knowledge of TCL, Unix, Shell, Linux, and physical build and verification EDA tools, along with strong attention to detail, self-motivation, and interpersonal skills.

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