Senior GPU Architect - Performance and Yield Optimization at NVIDIA

Department: Architect

Compensation

$184,000 – $287,500/yr

Setup: On-site
Location: California
Type: Full-time
Level: senior
Posted: Sep 15, 2026

Description

NVIDIA is hiring a GPU Architect to shape GPU architectures that improve product yield while maintaining performance and architectural simplicity. The role involves analyzing manufacturing defects, developing software tools and models for architectural constraints, optimizing large configuration spaces, designing multi-die architectures, and evaluating tradeoffs across yield, performance, area, cost, and complexity. Candidates need a BS, MS, or PhD in a relevant engineering or computer science field, at least 10 years of experience in GPU, CPU, SoC, or complex processor architecture, and strong C++ or Python skills. The base salary range is 184,000 USD to 287,500 USD for Level 4 and 224,000 USD to 356,500 USD for Level 5, with equity and benefits; applications were accepted until September 19, 2026.

Required Skills

GPU architecture
C++
Python
Computer architecture
Constraint reasoning
Combinatorial optimization
Multi-die architecture
Silicon yield

Additional Information

Minimum Education: Bachelor's, master's, or PhD in Computer Engineering, Computer Science, Electrical Engineering, or a related field, or equivalent experience
Required Previous Experiences: 10+ years of experience in GPU, CPU, SoC, or complex processor architecture
Experience building architectural models, simulators, optimization frameworks, or engineering analysis tools
Experience translating architecture and product requirements into rules, constraints, algorithms, and executable analysis
Preferred Qualifications: Hands-on GPU or large-scale SoC architecture experience
Experience with constraint-based reasoning, combinatorial optimization, or mathematical optimization
Background with silicon yield, defect tolerance, harvesting, redundancy, repair, resource isolation, or configurable processor architectures
Experience with multi-die, chiplet, or modular processor architectures and complex resource allocation
Experience with silicon or manufacturing data, performance or architecture simulators, GPU workload profiling, or production silicon