Senior GPU Floorplan Design Engineer at NVIDIA

Department: Engineer, ASIC

Setup: On-site
Location: Bengaluru, Karnataka
Type: Full-time
Level: senior
Posted: Jun 25, 2026

Description

NVIDIA is hiring a GPU Floorplan design Engineer in Bangalore to develop and optimize floorplans during early GPU development, collaborate with architecture and physical design teams, address timing and routing congestion, and build tools to improve chip area and execution speed. The role requires a B.Tech. or M.Tech. with at least five years of experience in floorplan, SOC planning, ASIC physical design, or related areas, along with VLSI or computer architecture expertise, hardware-level programming, and experience with physical design flows and chip implementation.

Required Skills

Floorplan
VLSI
Computer Architecture
Verilog
System Verilog
Python
C/C++
Timing
Congestion
Power Distribution
P&R

Additional Information

Minimum Education: B.Tech. or M.Tech.
Required Previous Experiences: 5+ years of experience in floorplan, SOC planning, ASIC physical design, or related roles
Hands-on experience with chip-level or subsystem-level floorplanning and physical planning
Experience with Verilog, System Verilog, or similar hardware description languages
Experience with CAD and physical design methodologies, chip floorplan, power and clock distribution, packaging, P&R, and timing closure
Experience with Python, Perl, and C/C++ programming
Preferred Qualifications: Experience driving development of large-scale ASIC floorplans
Translation Company Name: NVIDIA