Description
Arm is seeking a highly experienced ASIC Physical Design Engineer with at least 12 years of hands-on experience in full-chip and hierarchical SoC physical design. The role leads floor planning, partitioning, pin and IO planning, bump routing, power planning, CTS, clock architecture, physical verification, ESD planning, full-chip closure, and tape-out activities, while collaborating with RTL, synthesis, STA, package, and backend teams and mentoring junior engineers. The position requires a bachelor’s or master’s degree in a relevant engineering field and hands-on experience with leading EDA tools; advanced-node experience is preferred.
