Description
Arm is hiring a Solutions Engineering Physical IP Engineer to develop and validate custom standard-cell layouts for sub-3nm FinFET/GAA-based logic libraries. The role involves translating circuit schematics into optimized layouts, performing DRC and LVS sign-off, debugging physical issues, handling cell abutment and integration constraints, addressing layout-dependent effects and double-patterning/EUV compliance, and automating layout QA and regression checks with Python, SKILL, PERL, and TCL. The position requires at least three years of custom layout experience and proficiency with Cadence Virtuoso, advanced physical verification, and PPA optimization.
