Description
The Senior Lead RTL Engineer will design and develop RTL in Verilog or SystemVerilog for ASIC and SoC projects, define module- and micro-architecture, collaborate with verification, synthesis, and physical design teams, drive RTL quality through linting, clock-domain crossing, and synthesis readiness, support complex SoC integration and debugging, mentor junior engineers, and work with global teams in India and Japan. The role requires strong RTL design, SoC architecture, synthesis, and timing awareness, with low-power, DFT, and CDC knowledge preferred.
