Description
The Digital Physical Design Engineer is responsible for complete STA signoff for a system-on-chip or subsystem, including timing constraint development, constraint validation, interaction with frontend, DFT, and IP teams, and timing signoff through tapeout. The role requires AI exposure in STA activities, SDF generation and validation, SI closure, experience with advanced technology nodes such as 16nm and 5nm, and strong knowledge of physical design flows, placement, clock-tree synthesis, and routing. The engineer also contributes to physical design problem solving and technology-node strategy.
