Description
SiTime Corporation, a precision timing company, is seeking a Senior Logic Design Engineer to develop digital designs for CMOS dies. The engineer will be responsible for micro-architecture specification, RTL design using Verilog/SystemVerilog, test bench development, timing constraints, synthesis, and post-Si validation. The role requires a Master’s degree in electrical engineering with 5 years of relevant experience, proficiency in Verilog/SystemVerilog, and expertise in digital logic design.
