Description
Astera Labs is hiring a Senior Manager/Manager, Digital Design to lead front-end digital design for high-performance PCIe, CXL, UAL, and Ethernet devices used in rack-scale AI infrastructure. The role owns chip development from requirements and architecture through RTL, verification, physical design, tape-out, and shipment; leads at least two complex devices; establishes RTL quality and tape-out readiness practices; and manages a team of 6–8 digital design engineers while coordinating with architecture, verification, physical design, DFT, firmware, validation, and operations teams. The position requires a bachelor’s degree in a relevant technical field, 3–5 years of engineering management or technical leadership experience, and demonstrated ownership of chip design through tape-out and shipment. The salary range is $216,000 to $240,000, with possible discretionary bonus, incentives, and benefits.
